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general description the max9322 low-skew 1:15 differential clock driverreproduces or divides one of two differential input clocks at 15 differential outputs. an input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0ghz. the 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function. the max9322 operates in lvpecl systems with a +2.375v to +3.8v supply or in lvecl systems with a -2.375v to -3.8v supply. a v bb reference output pro- vides compatibility with single-ended clock input sig- nals and a master reset input provides a simultaneous reset on all outputs. the max9322 is available in 52-pin tqfp and 68-pin qfn packages and is specified for operation over -40? to +85?. for 1:10 clock drivers, refer to the max9311/max9313 data sheet. for 1:5 clock drivers, refer to the max9316 data sheet. applications precision clock distributionlow-jitter data repeaters central-office backplane clock distribution dslam backplane base stations ate features ? 1.2ps (rms) maximum random jitter ? 300mv differential output at 1.0ghz ? 900ps propagation delay ? selectable divide-by-1 or divide-by-2 frequencyoutputs ? multiplexed 2:1 input function ? lvecl operation from v ee = -2.375v to -3.8v ? lvpecl operation from v cc = +2.375v to +3.8v ? esd protection: > 2kv human body model max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver ________________________________________________________________ maxim integrated products 1 32 tqfp top view 27 52 vcco 51 qa0 50 qa0 49 qa1 48 qa1 47 vcco 46 qb0 45 qb0 44 qb1 43 qb1 42 qb2 41 qb2 40 vcco vcco 14 qd5 15 qd5 16 qd4 17 qd4 18 qd3 19 qd3 20 qd2 21 qd1 23 qd2 22 qd1 24 qd0 26 qd0 25 vcco 28 n.c. 29 n.c. 30 vcco 31 qc3 qc3 34 qc2 33 qc2 35 qc1 36 qc1 37 qc0 38 qc0 39 vcco fseld 12 v ee 13 fselc 11 v bb 10 clk1 9 clk1 8 clk_sel 7 clk0 6 clk0 5 fsela 3 fselb 4 mr 2 v cc 1 max9322 pin configurations ordering information typical operating circuit 19-2544; rev 2; 2/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max9322ecy -40 c to +85 c 52 tqfp max9322etk* -40 c to +85 c 68 qfn * future product?ontact factory for availability. 50 ? 50 ? max9322 z o = 50 ? z o = 50 ? receiver q_q_ v tt = v cc - 2.0v pin configurations continued at end of data sheet. downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to v ee .............................................................................4.1v inputs and outputs to v ee ..........................-0.3v to (v cc + 0.3v) differential input magnitude............lower of (v cc - v ee ) and 3v continuous output current .................................................50ma surge output current........................................................100ma v bb sink/source current ...............................................?.65ma continuous power dissipation (t a = +70?) single-layer pc board 52-pin tqfp (derate 15.4mw/? above +70?).....1230.8mw 68-lead qfn (derate 27.8mw/? above +70?) ...2222.2mw multilayer pc board 52-pin tqfp (derate 19.1mw/? above +70?).....1529.6mw 68-lead qfn (derate 38.5mw/? above +70?) ...3076.9mw junction-to-ambient thermal resistance in still air single-layer pc board 52-pin tqfp...............................................................+65?/w 68-lead qfn .............................................................+36?/w multilayer pc board 52-pin tqfp............................................................+52.3?/w 68-lead qfn .............................................................+26?/w junction-to-ambient thermal resistance with 500 lfpm airflow single-layer pc board 52-pin tqfp...............................................................+50?/w 68-lead qfn .............................................................+27?/w multilayer pc board 52-pin tqfp...............................................................+40?/w 68-lead qfn .............................................................+20?/w junction-to-case thermal resistance 52-pin tqfp............................................................+12.9?/w 68-lead qfn ...............................................................+2?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? esd protection human body model (q_ _, q_ _ , clk_sel, fsel_, clk_ , clk_, mr, v bb ) ............................................?kv soldering temperature (10s) ...........................................+300? dc electrical characteristics((v cc - v ee ) = 2.375v to 3.8v, outputs loaded with 50 ? ?% to v cc - 2v; clk_sel, fsel_ = high or low; mr = low; |v id | = 0.095v to the lower of (v cc - v ee ) and 3v. typical values are at (v cc - v ee ) = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v.) (notes 1?) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units single-ended input (mr, fsel_, clk_sel) input high voltage v ih1 figure 1 v cc - 1.155 v cc - 0.88 v cc - 1.155 v cc - 0.88 v cc - 1.155 v cc - 0.88 v input low voltage v il1 figure 1 v cc - 1.81 v cc - 1.505 v cc - 1.81 v cc - 1.505 v cc - 1.81 v cc - 1.505 v input current i in1 mr, fsel_, clk_sel= v il or v ih -15 +150 -15 +150 -15 +150 ? differential input (clk_, clk_ ) single-ended inputhigh voltage v ih2 figure 1 v cc - 1.155 v cc - 0.88 v cc - 1.155 v cc - 0.88 v cc - 1.155 v cc - 0.88 v single-ended inputlow voltage v il2 figure 1 v cc - 1.81 v cc - 1.505 v cc - 1.81 v cc - 1.505 v cc - 1.81 v cc - 1.505 v high voltage ofdifferential input v ihd v ee + 1.2 v cc v ee + 1.2 v cc v ee + 1.2 v cc v low voltage ofdifferential input v ild v ee v cc - 0.095 v ee v cc - 0.095 v ee v cc - 0.095 v downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver _______________________________________________________________________________________ 3 dc electrical characteristics (continued)((v cc - v ee ) = 2.375v to 3.8v, outputs loaded with 50 ? ?% to v cc - 2v; clk_sel, fsel_ = high or low; mr = low; |v id | = 0.095v to the lower of (v cc - v ee ) and 3v. typical values are at (v cc - v ee ) = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v.) (notes 1?) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units for v cc - v ee < 3.0v 0.095 v cc - v ee 0.095 v cc - v ee 0.095 v cc - v ee differential inputvoltage v ihd - v ild for v cc - v ee 3.0v 0.095 3.0 0.095 3.0 0.095 3.0 v input current i in2 clk_, clk_ = v ihd or v ild -150 +150 -150 +150 -150 +150 ? outputs (q_, q_ ) single-endedoutput high voltage v oh figure 1 v cc - 1.085 v cc - 0.880 v cc - 1.025 v cc - 0.880 v cc - 1.025 v cc - 0.880 v single-endedoutput low voltage v ol figure 1 v cc - 1.810 v cc - 1.52 v cc - 1.810 v cc - 1.620 v cc - 1.810 v cc - 1.620 v differential outputvoltage v oh - v ol figure 1 500 600 600 mv reference reference voltageoutput v bb i bb = 0.5ma (note 5) v cc - 1.41 v cc - 1.25 v cc - 1.41 v cc - 1.25 v cc - 1.41 v cc - 1.25 v supply supply current i ee (note 6) 50 85 66 115 80 130 ma downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver 4 _______________________________________________________________________________________ note 1: measurements are made with the device in thermal equilibrium. note 2: current into a pin is defined as positive. current out of a pin is defined as negative. note 3: single-ended clk_, clk_ input operation is limited to v cc - v ee = 3.0v to 3.8v. note 4: dc parameters are production tested at t a = +25? and guaranteed by design over the full operating temperature range. note 5: use v bb as a reference for inputs of the same device only. note 6: all pins open except v cc and v ee . note 7: guaranteed by design and characterization. limits are set at ? sigma. note 8: measured between outputs of the same parts at the signal crossing points under identical conditions for a same-edge transition. note 9: device jitter added to a jitter-free input signal. ac electrical characteristics((v cc - v ee ) = 2.375v to 3.8v; outputs loaded with 50 ? ?% to v cc - 2v; input frequency 1000mhz; input transition time = 125ps (20% to 80%); clk_sel, fsel_ = high or low, mr = low; v ihd = v ee + 1.2v to v cc ; v ild = v ee to v cc - 0.4v; v ihd - v ild = 0.4v to 1v. typical values are at (v cc - v ee ) = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v.) (note 7) -40 c +25 c +85 c parameter symbol condition min typ max min typ max min typ max units differential input-to-output delay t plhd , t phld figure 2 700 900 1150 725 900 1180 750 950 1225 ps single-endedclk_/ clk_ to output delay t phls , t plhs figure 1 700 900 1170 700 900 1175 725 950 1250 ps mr to outputdelay t pd figure 3 450 930 450 930 450 930 ps output-to-outputskew t skoo (note 8) 85 56 50 ps added randomjitter t rj f in = 1.0ghz clock pattern(note 9) 1.2 1.2 1.2 ps (rms) addeddeterministic jitter t dj 1gbps 2 23 - 1 prbs pattern(note 9) 61 61 61 ps p-p switchingfrequency f max v od > 300mv 1.0 1.0 1.0 ghz differential outputrise and fall time (20% to 80%) t r , t f figure 2 200 260 400 200 260 400 200 240 400 ps downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver _______________________________________________________________________________________ 5 max9322 toc01 temperature ( c) supply current (ma) 60 35 10 -15 45 55 65 75 8535 -40 85 supply current, i ee vs. temperature max9322 toc02 frequency (mhz) output amplitude (mv) 800 600 400 1400 1200 1000 200 100 200 300 400 500 600 700 800 0 0 1600 output amplitude, v oh - v ol vs. frequency transition time vs. temperature max9322 toc03 temperature ( c) transition time (ps) 60 35 10 -15 210 220 230 240 250 260 270200 -40 85 t f t r max9322 toc04 v ihd - v ee (v) propagation delay (ps) 3.0 2.7 2.4 2.1 1.8 1.5 885 890 895 900 905 910880 1.2 3.3 propagation delay vs. high voltage of differential input, v ihd max9322 toc05 temperature ( c) propagation delay (ps) 60 35 10 -15 940 960 980880 900 920 1000 1020 860 -40 85 propagation delay vs. temperature single-ended clock differential clock v ih2 = v cc = 1.15v v il2 = v cc = 1.48v 750 790 830 870 910 950 01 . 0 0.5 1.5 2.0 2.5 3.0 propagation delay vs. differential input voltage max9322 toc06 differential input voltage (vihd - vild) (v) propagation delay (ps) typical operating characteristics (v cc - v ee = 3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, v id = 500mv, clk_sel = 0, fsel_ = 0, f in = 600mhz, t a = +25?, unless otherwise noted.) downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver 6 _______________________________________________________________________________________ pin description pin tqfp qfn name function 1 2, 3 v cc positive power supply. powers input circuitry. bypass each v cc to v ee with a 0.01? and 0.1? capacitor. place the capacitors as close to the device as possible with thesmaller value capacitor closest to the device. 24m r single-ended master reset. a high on mr sets all outputs to differential zero. a low onmr enables all outputs. mr is pulled to v ee through a 75k ? resistor. 35 fsela single-ended frequency select a. selects the output frequency for bank a. bank aconsists of two differential outputs. a low on fsela selects divide-by-1. a high on fsela selects divide-by-2. fsela is pulled to v ee through a 75k ? resistor. 46 fselb single-ended frequency select b. selects the output frequency for bank b. bank bconsists of three differential outputs. a low on fselb selects divide-by-1. a high on fselb selects divide-by-2. fselb is pulled to v ee through a 75k ? resistor. 5 7 clk0 noninverting clock 0 input. clk0 is pulled to v ee through 75k ? resistors. 68 clk0 inverting clock 0 input. clk0 is pulled to v cc and to v ee through a 75k ? resistor. 79 clk_sel single-ended clock selector input. a low on clk_sel selects clk0. a high onclk_sel selects clk1. clk_sel is pulled to v ee through a 75k ? resistor. 8 10 clk1 noninverting clock 1 input. clk1 is pulled to v ee through a 75k ? resistor. 91 1 clk1 inverting clock 1 input. clk1 is pulled to v cc and to v ee through 75k ? resistors. 10 12 v bb reference voltage output. connect v bb to clk_ or clk_ to provide a reference for single-ended operation. when used, bypass with a 0.01? ceramic capacitor to v cc ; otherwise leave open. 11 13 fselc single-ended frequency select c. selects the output frequency for bank c. bank cconsists of four differential outputs. a low on fselc selects divide-by-1. a high on fselc selects divide-by-2. fselc is pulled to v ee through a 75k ? resistor. 12 14 fseld single-ended frequency select d. selects the output frequency for bank d. bank dconsists of six differential outputs. a low on fseld selects divide-by-1. a high on fseld selects divide-by-2. fseld is pulled to v ee through a 75k ? resistor. 13 15, 16 v ee negative power-supply input 14, 27, 30,39, 40, 47, 52 19, 20, 33,36, 37, 40, 49, 50, 53, 54, 61, 66, 67 v cco output driver positive power supply. powers device output drivers. bypass each v cco to v ee with a 0.01? and 0.1? capacitor. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 15 21 qd5 inverting qd5 output. typically terminate with 50 ? resistor to v cc - 2v. 16 22 qd5 noninverting qd5 output. typically terminate with 50 ? resistor to v cc - 2v. 17 23 qd4 inverting qd4 output. typically terminate with 50 ? resistor to v cc - 2v. 18 24 qd4 noninverting qd4 output. typically terminate with 50 ? resistor to v cc - 2v. downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver _______________________________________________________________________________________ 7 pin description (continued) pin tqfp qfn name function 19 25 qd3 inverting qd3 output. typically terminate with 50 ? resistor to v cc - 2v. 20 26 qd3 noninverting qd3 output. typically terminate with 50 ? resistor to v cc - 2v. 21 27 qd2 inverting qd2 output. typically terminate with 50 ? resistor to v cc - 2v. 22 28 qd2 noninverting qd2 output. typically terminate with 50 ? resistor to v cc - 2v. 23 29 qd1 inverting qd1 output. typically terminate with 50 ? resistor to v cc - 2v. 24 30 qd1 noninverting qd1 output. typically terminate with 50 ? resistor to v cc - 2v. 25 31 qd0 inverting qd0 output. typically terminate with 50 ? resistor to v cc - 2v. 26 32 qd0 noninverting qd0 output. typically terminate with 50 ? resistor to v cc - 2v. 28, 29 1, 17, 18, 34, 35, 38, 39, 51, 52, 68 n.c. no connection. not internally connected. 31 41 qc3 inverting qc3 output. typically terminate with 50 ? resistor to v cc - 2v. 32 42 qc3 noninverting qc3 output. typically terminate with 50 ? resistor to v cc - 2v. 33 43 qc2 inverting qc2 output. typically terminate with 50 ? resistor to v cc - 2v. 34 44 qc2 noninverting qc2 output. typically terminate with 50 ? resistor to v cc - 2v. 35 45 qc1 inverting qc1 output. typically terminate with 50 ? resistor to v cc - 2v. 36 46 qc1 noninverting qc1 output. typically terminate with 50 ? resistor to v cc - 2v. 37 47 qc0 inverting qc0 output. typically terminate with 50 ? resistor to v cc - 2v. 38 48 qc0 noninverting qc0 output. typically terminate with 50 ? resistor to v cc - 2v. 41 55 qb2 inverting qb2 output. typically terminate with 50 ? resistor to v cc - 2v. 42 56 qb2 noninverting qb2 output. typically terminate with 50 ? resistor to v cc - 2v. 43 57 qb1 inverting qb1 output. typically terminate with 50 ? resistor to v cc - 2v. 44 58 qb1 noninverting qb1 output. typically terminate with 50 ? resistor to v cc - 2v. 45 59 qb0 inverting qb0 output. typically terminate with 50 ? resistor to v c c - 2v. 46 60 qb0 noninverting qb0 output. typically terminate with 50 ? resistor to v cc - 2v. 48 62 qa1 inverting qa1 output. typically terminate with 50 ? resistor to v cc - 2v. 49 63 qa1 noninverting qa1 output. typically terminate with 50 ? resistor to v cc - 2v. 50 64 qa0 inverting qa0 output. typically terminate with 50 ? resistor to v cc - 2v. 51 65 qa0 noninverting qa0 output. typically terminate with 50 ? resistor to v cc - 2v. ? pv ee the exposed pad of the qfn package is internally connected to v ee . refer to application note hfan-08.1. downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver 8 _______________________________________________________________________________________ clk_ clk_q_ v oh v ol v ih2 v il2 v bb v oh - v ol t phls t plhs mr, fsel_, clk_sel v ih1 v il1 v bb (clk_ is connected to v bb ) q_ figure 1. timing diagram for single-ended inputs clk_clk_ q_ t plhd t phld v ihd - v ild v ihd v ild 0v (differential) 0v (differential) 20% 80% 20% 80% t r t f v ol v oh v oh - v ol q_ q_ - q_ v oh - v ol figure 2. timing diagram for differential inputs downloaded from: http:///
detailed description the max9322 low-skew 1:15 differential clock driverreproduces or divides one of two differential input clocks at 15 differential outputs. an input multiplexer selects from one of two input clocks with input frequen- cy operation in excess of 1.0ghz. the 15 outputs are arranged into four banks with 2, 3, 4, and 6 outputs, respectively. each output bank is individually program- mable to provide a divide-by-1 or divide-by-2 frequen- cy function. lvecl/lvpecl operation output levels are referenced to v cc and are lvpecl or lvecl, depending on the level of the v cc supply. with v cc connected to a positive supply and v ee connected to ground, the outputs are lvpecl. the outputs arelvecl when v cc is connected to ground and v ee is connected to a negative supply. when interfacing todifferential lvpecl signals, the v cc range is 2.375v to 3.8v (v ee = 0), allowing high-performance clock distri- bution in systems with nominal 2.5v and 3.3v supplies.when interfacing to differential lvecl, the v ee range is -2.375v to -3.8v (v cc = 0). control inputs (fsel_, clk_sel, mr) the max9322 provides four output banks: a, b, c, andd. bank a consists of two differential output pairs. bank b consists of three differential output pairs. bank c consists of four differential output pairs. bank d con- sists of six differential output pairs. fsel_ selects the output clock frequency for a bank. a low on fsel_ selects divide-by-1 frequency operation while a high on fsel_ selects divide-by-2 operation. clk_sel selects clk0 or clk1 as the input signal. a low on clk_sel selects clk0 while a high selects clk1. master reset (mr) enables all outputs. clk_sel and fsel_ are asynchronous. changes to the control inputs (clk_sel, fsel_) or on power-up cause indeterminate output states requiring a mr assertion to resynchronize any divide-by-2 outputs (figure 4). a low on mr activates all outputs for normal operation. a high on mr resets alloutputs to differential low condition. see table 1. input termination resistors differential inputs clk_ and clk_ are biased to guar- antee a known state (differential low) if the inputs areleft open. clk_ is internally pulled to v ee through a 75k ? resistor. clk_ is internally pulled to v cc and to v ee through 75k ? resistors. single-ended inputs fsel_, mr, and clk_sel areinternally pulled to v ee through a 75k ? resistor. differential clock input the max9322 accepts two differential or single-endedclock inputs, clk0/ clk0 and clk1/ clk1 . clk_sel selects between clk0/ clk0 and clk1/ clk1 . a low on clk_sel selects clk0/ clk0 . a high on clk_sel selects clk1/ clk1 . see table 1. differential clk_ inputs must be at least v bb ?5mv to switch the outputs to the v oh and v ol levels specified in the dc electrical characteristics table. the maximum magnitude of the differential signal applied to the differ-ential clock input is the lower of (v cc - v ee ) and 3.0v. this limit also applies to the difference between any ref-erence voltage input and a single-ended input. specifications for the high and low voltages of a differ- ential input (v ihd and v ild ) and the differential input voltage (v ihd - v ild ) apply simultaneously. max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver mr q_ q_ t pd v ih v il v ol v oh v bb function pin low or open high fsel_ divide-by-1 divide-by-2 clk_sel clk0 clk1 mr* active reset table 1. function table * a master reset is required following power-up or changes to input functions to prevent indeterminant output states. figure 3. timing diagram for mr _______________________________________________________________________________________ 9 downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver 10 ______________________________________________________________________________________ clk_ mr q_( 1) q_( 2) figure 4. timing diagram for mr resynchronization single-ended inputs and v bb the differential clock input can be configured to accepta single-ended input when operating at v cc - v ee = 3.0v to 3.8v. connect v bb to the inverting or noninvert- ing input of the differential input as a reference for sin- gle-ended operation. the differential clk_ input is converted to a noninverting, single-ended input by con- necting v bb to clk_ and connecting the single-ended input signal to clk. similarly, an inverting configurationis obtained by connecting v bb to clk_ and connecting the single-ended input to clk_ . the single-ended inputs fsel_, clk_sel, and mr areinternally referenced to v bb . all single-ended inputs (fsel_, clk_sel, mr, and any clk_ in single-endedmode) can be driven to v cc and v ee or with a single- ended lvpecl/lvecl signal. the single-ended inputmust be at least v bb ?5mv to switch the outputs to the v oh and v ol levels specified in the dc electrical characteristics table. when using the v bb reference output, bypass v bb with a 0.01? ceramic capacitor to v cc . leave v bb open when not used. the v bb refer- ence can source or sink 0.5ma. use v bb as a refer- ence for the same device only. applications information supply bypassing bypass each v cc and v cco to v ee with high-frequency surface-mount ceramic 0.01? and 0.1? capacitors inparallel as close to the device as possible, with the 0.01? capacitor closest to the device. use multiple parallel vias to minimize parasitic inductance. when using the v bb reference output, bypass v bb to v cc with a 0.01? ceramic capacitor. controlled-impedance traces input and output trace characteristics affect the perfor-mance of the max9322. connect input and output sig- nals with 50 ? characteristic impedance traces. minimize the number of vias to prevent impedance dis-continuities. reduce reflections by maintaining the 50 ? characteristic impedance through cables and connec-tors. reduce skew within a differential pair by matching the electrical length of the traces. output termination terminate outputs with 50 ? to v cc - 2v or use an equivalent thevenin termination. when a single-endedsignal is taken from a differential output, terminate both outputs. for example, if qa0 is used as a single-ended output, terminate both qa0 and qa0 . downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver ______________________________________________________________________________________ 11 0 1 0 1 0 1 0 1 1 2 75k ? 75k ? 75k ? v ee v cc v ee 75k ? 75k ? 75k ? v ee v cc v ee 75k ? v ee 75k ? v ee 75k ? v ee 75k ? v ee 75k ? v ee 75k ? v ee fsela clk0clk0 clk1 clk1 clk_sel mr fselb fselcfseld v bb bank abank b bank c bank d qa0qa0 qa1 qa1 qb0 qb0 qb1 qb1 qb2 qb2 qc0 qc0 qc1 qc1 qc2 qc2 qc3 qc3 qd0 qd0 qd1 qd1 qd2 qd2 qd3 qd3 qd4 qd4 qd5 qd5 max9322 functional diagram downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver 12 ______________________________________________________________________________________ 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 clk1 vcco qa1 qfn* top view qa1vcco qb0 qb0 qb1 qb1 qb2 qb2 vcco 52 53 vcco n.c. n.c.qd5 vcco qd4 qd5qd3 qd4qd2 qd3qd1 qd2qd0 qd1qd0 qc0qc1 qc1 qc2 qc2 qc3qc3 vcco n.c. n.c. 35 36 37 vcco vcco n.c. clk1 clk_sel clk0 clk0 fselb v ee v ee fseld fselc v bb fsela mr v cc v cc 48 qc0 n.c. 64 qa0 6566 67 vccovcco qa0 68 n.c. 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 vcco n.c. 34 33 49 50 vccovcco 51 n.c. 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 n.c. 17 max9322 the exposed pad of the qfn package must be soldered to v ee for proper thermal and electrical operation of the max9322. pin configurations (continued) chip information transistor count: 2063process: bipolar downloaded from: http:///
max9322 lvecl/lvpecl 1:15 differential divide-by-1/divide-by-2 clock driver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package outline 52l tqfp, 10x10x1.0 mm 1 1 21-0146 a rev. document control no. approval proprietary information title: top view 0.65 bsc nom 0.10 - - 0.32 12.00 10.00 bsc 10.00 bsc 0.60 12.00 e 0.45 l 11.80 ee1 d1 dim 11.80 0.09 0.05 cd a1b min - a 0.75 12.20 0.150.20 12.20 1.20 max a2 0.95 1.00 1.05 seating plane e1 a1 a2 see detail "a" 52 c a 1 see 4 e1 b e 4 d1 d1 d gage plane 1.00 ref detail a l 0-7 0.25 0 min. e 0.22 0.38 note 2 52l tqfp.eps revision history pages changed at rev 2: 1, 5, 13 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) downloaded from: http:///

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